-- Top HDL entity

library IEEE;
use IEEE.std_logic_1164.all;

entity TOP is
	port
	(
		clk       : in std_logic;
		reset     : in std_logic;
		speed     : in std_logic_vector (7 downto 0);
		PWMout    : out std_logic;
		PWMout2   : out std_logic
	);
end TOP;


ARCHITECTURE design of TOP is

SIGNAL clk227Mhz : std_logic;
SIGNAL PWM       : std_logic;

BEGIN

clk1 : entity work.clk(design)		-- 50 Mhz -> 2.27Mhz
	port map
	(
		clk50Mhz  => clk,
		reset     => reset,
		clk227Mhz => clk227Mhz
	);
				
PWM1 : entity work.PWM(design)
	port map
	(
		clk   => clk227Mhz,
		reset => reset,
		PWM   => PWM,
		speed => speed
	);
				
PWMout  <= PWM;
PWMout2 <= PWM;
--PWMout <= '1'; -- Debugging as constant high

END design;